1. Field of the Invention
The present invention relates to a method for forming a multilayer structure, a method for manufacturing a display panel, and a display panel.
2. Description of the Related Art
In recent years, active matrix type liquid crystal display panels that employ a thin film transistor (TFT) as a switching element have been developed. On the display area of the active matrix type liquid crystal display panel, there are provided a plurality of pixels arranged in a matrix. That is, on one of two substrates arranged to face each other, a plurality of pixel electrodes are arranged in a matrix. Each of the plurality of pixels electrodes is connected to either one of a source electrode and a drain electrode of the respective corresponding thin film transistor. The other one of the source electrode and the drain electrode of the thin film transistor is connected to a signal line that extends in the column direction. In addition, a gate electrode in the thin film transistor is connected to a scanning line that extends in the row direction.
Here, the signal line and the scanning line are formed as different layers with respect to each other via a first insulating layer between the signal line and the scanning line. That is, by forming the signal line and the scanning line as different conductive layers with respect to each other, the signal line and the scanning line will not be shorted in regions of intersections thereof and can be respectively formed to extend in directions perpendicular to each other.
As the thin film transistor, an inversely-staggered type and a coplanar type are known. For example, in the inversely-staggered type thin film transistor, the gate electrode thereof is formed as a first conductive layer that is located on the substrate side opposite to the semiconductor thin film side, and the source/drain electrode is formed as a second conductive layer that is located on a liquid crystal side opposite to the semiconductor thin film side. Therefore, when the inversely-staggered type is used as the thin film transistors, the scanning lines that are connected to the gate electrodes is formed of the same first conductive layer as the gate electrodes, and the signal lines are formed of the same second conductive layer as the source/drain electrodes.
The thin film transistor and the signal line are covered with a planarization film as a second insulating layer, which is deposited on an upper layer side thereof (the liquid crystal layer side). Accordingly, in order to electrically connect the first conductive layer to a third conductive layer that is formed on the second insulating layer, a part of the first conductive layer needs to be exposed by forming a contact hole through the first insulating layer and the second insulating layer. In this case, the contact hole formed in the first insulating layer and the contact hole formed in the second insulating layer are formed at once by the same photolithography process so as to communicate with each other.
However, even when the first insulating layer and the second insulating layer are formed of the same material, as shown in FIG. 20, it is recognized that the cross-section shape of the contact hole 61 in the second insulating layer 63 is formed in a reverse tapered shape while the cross-sectional shape of the contact hole 61 in the first insulating layer 62 is formed in a tapered shape. The cause of this anomaly is considered as follows. When the second conductive layer 64 is formed and/or patterned on the first insulating layer 62, the surface condition of the first insulating layer 62 changes. This change in the surface condition causes the boundary between the first insulating layer 62 and the second insulating layer 63 more susceptible to etching—i.e., the etching rate of the insulating layers 62,63 is faster near the boundary between these two insulating layers during the formation of the contact hole 61. More specifically, it is considered that the altered boundary layer on the first insulating layer 62 is etched from the exposed edge first, and, as a result, the surface of the second insulating layer 63 that is facing the first insulating layer 62 is exposed. Accordingly, the second insulating layer 62 is also etched from the exposed surface.
When the second insulating layer 63 is formed in the reverse tapered shape as described above, a third conductive layer 65, which is formed on the second insulating layer 63 to make contact with the first conductive layer 66 within the contact hole 61, cannot appropriately cover the contour of contact hole 61, leaving discontinued portions in the third conductive layer 65 as shown in FIG. 20. In other words, the coverage of the third conductive layer 65 along the contour of the contact hole 61 is not adequate. This results in connection error between the third conductive layer 66 and the first conductive layer 65.